1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device with a high withstand-voltage transistor formed on a semiconductor substrate, and a fabricating method thereof.
2. Description of the Related Art
FIG. 2A to FIG. 2C are fabrication process drawings for the conventional semiconductor devices as stated in Japanese Patent Laid-Open Publication No. 3-204939, Patent Laid-Open Publication No. 5-267334, and Japanese Patent Laid-Open Publication No. 6-333948. Any of these illustrates a fabricating method for a transistor of an LDD (Lightly Doped Drain) structure in which the low concentration impurity region is given on the gate electrode side in the source/drain region. The transistor of LDD structure features that the width of a depletion layer formed between the channel region and the source/drain region is increased for decreasing the potential gradient and lowering the drain current in the off-state.
FIG. 2A is a figure as given in Japanese Patent Laid-Open Publication No. 3-204939. At step 1, a gate oxide film 12 and a polysilicon layer 13 are formed on a p-type silicon substrate 11, and on this polysilicon layer 13, a natural oxide film 14 is formed, then a high melting-point metal layer 15, such as tungsten, or the like, is deposited, and a pattern of a photoresist 19 is formed. Next, the photoresist 19 and the natural oxide film 14 are used as a mask and an etching stopper, respectively, to anisotropically etch the high melting-point metal layer 15 for formation of a second gate electrode 15a made of a high melting-point metal.
At step 2, the photoresist 19 is removed, and a low concentration of an n-type impurity is implanted into the p-type silicon substrate 11, using the gate electrode 15a as a mask, to form an n-diffusion layer 17. Further, over the entire surfaces of the natural oxide film 14 and the gate electrode 15a, a silicon oxide film 16 is deposited.
At step 3, the silicon oxide film 16 is etched back, forming a side wall 16a made of an oxide film. By this etchback, the natural oxide film 14 is also etched off except for the portion thereof that is adjacent to the gate electrode 15a and the oxide film side wall 16a. Thereafter, the polysilicon layer 13 is etched, using the gate electrode 15a and the oxide film side wall 16a as a mask, to form a first gate electrode 13a made of polysilicon.
At step 4, using the second gate electrode 15a, the oxide film side wall 16a, and the first gate electrode 13a as a mask, a high concentration of an n-type impurity is implanted into the n-diffusion layer 17 to form an n+ diffusion layer 18. This n+ diffusion layer 18 provides source/drain regions for the transistor. Thereafter, application of a heat treatment will cause the high melting-point metal in the second gate electrode 15a to be thermally diffused into the natural oxide film 14, resulting in the first gate electrode 13a and the second gate electrode 15a being electrically connected to each other.
FIG. 2B is a figure as given in Japanese Patent Laid-Open Publication No. 5-267334. At step 1, on the main surface of a p-type silicon substrate 21, the LOCOS (Local Oxidation of Silicon) method is used to form a field oxide film 22 in an element isolation region, and a gate oxide film 23 in the element formation region. Next, on the surfaces of the field oxide film 22 and the gate oxide film 23, a polysilicon film 24 and a natural oxide film 25 are sequentially formed. Further, on the surface of the natural oxide film 25, an n-type polysilicon layer, which provides a gate electrode constituting material, is deposited, and this polysilicon layer is dry etched by photolithography for forming a second polysilicon film 26. In this dry etching, the natural oxide film 25 serves as an etching stopper. In this state, using the second polysilicon film 26 as a mask, a low concentration of an n-type impurity is implanted into the p-type silicon substrate 21 to form an n-type low concentration layer 27.
At step 2, a silicon nitride film is deposited, and this silicon nitride film is etched to form a first side wall 28a on the side face of the second polysilicon film 26. Further, using the polysilicon film 26 and the side wall 28a as a mask, the natural oxide film 25 and the polysilicon film 24 are sequentially dry etched. Thereby, a natural oxide film 25a and a polysilicon film 24a which provide a gate electrode are formed.
At step 3, after selectively removing the first side wall 28a, a silicon dioxide film is deposited, and this silicon dioxide film is etched to form a second side wall 29.
At step 4, a high concentration of an n-type impurity is implanted into the n-type low concentration layer 27 to form an n-type high concentration layer 30, which provides source/drain regions.
FIG. 2C is a figure as given in Japanese Patent Laid-Open Publication No. 6-333948. At step 1, a semiconductor thin film 32 made of silicon, or the like, is formed on an insulation substrate 31, on the surface thereof, a gate oxide film 33 is formed, and further on the surface thereof, a gate electrode film 34 for formation of a gate electrode is formed.
At step 2, using a resist film 35 as a mask, the gate electrode film 34 is dry etched to form a gate electrode 34a. At this time, the width of the gate electrode 34a is made narrower than that of the resist film 35 by side etching.
At step 3, using the resist film 35 as a mask, the gate insulation film 33 is partially anisotropically etched to form a shoulder part in a location which provides a broader width than that of the gate electrode 34a. Thereby, a gate insulation film 33a is formed which is different in film thickness, the area under the gate electrode 34a being made thicker, while the area other than that being made thinner.
At step 4, after removing the resist film 35, an impurity is implanted into the semiconductor thin film 32 to form source/drain regions 36. The amount of implantation of the impurity depends upon the film thickness of the gate insulation film, resulting in the portion closer to the gate electrode 34a providing a low concentration layer 36L which is low in impurity concentration, while the portion further away from the gate electrode 35a providing a high concentration layer 36H which is high in impurity concentration, thus an LDD structure can be obtained.
However, with the transistors as stated in the above three literatures, the amount of overlap between the low concentration layer and the gate electrode is small, thus there has been a problem that the capability of the low concentration layer as an electric field relaxation layer for enhancing the hot-carrier resistance is low, which makes it difficult for such transistors to accommodate high voltages.